Modern circuit design incorporates methods and hardware that enable circuit testing upon completion of production, often referred to as “design for test” or “design for testability” (DFT). One DFT technique utilizes scan chains. In a scan chain system, certain latches, independent of their assigned cone of logic, couple together into a hardware connection known as a “scan chain.” The test system inputs a test pattern into the scan chain latches, which the system then uses to test the functionality of the circuit. As such, scan chains allow for increased testability and observability of an integrated circuit design.
Many systems use multiple-input signature registers (MISRs) coupled to the scan chain outputs to generate a unique signature for specific test response sequence. The MISRs generate and store the resulting signature from the test responses. Typical systems compare the resulting signature with signatures of known good, fault-free circuits to determine whether the circuit under test (CUT) (also sometimes referred to as a “device under test” (DUT)) is functioning correctly. Generally, one skilled in the art will understand that the DUT also comprises a variety of circuitry in addition to the scan chains and MISRs.
Common test systems can generate the test sequences in multiple ways, including though automatic test pattern generation (ATPG) for targeted tests or through pseudo random pattern generators (PRPGs), such as linear feedback shift registers (LFSRs), for example. These test sequences can cover over 100,000 or more individual testing events that are compacted into a single signature within a MISR. Though the signature effectively reduces the total output data down to the width of the MISR (usually between 10 and 40 bits from 100,000×50,000), diagnosing fails within the system becomes significantly more difficult and time consuming as compaction increases.
Most current testing methodologies operate in a predictable manner. A PRPG supplies patterns to be pushed into the scan chains. A functional clock cycle activates and pushes these patterns through the CUT's logic. After a set number of functional clock cycles, the process serially feeds the state of every latch into a MISR through the scan chains. After all of the latch states have been scanned into the MISR, the testing process evaluates the resultant signature for correctness. In the event that the resultant signature is correct, the testing process takes no further action, as the CUT is working properly. In the event that the resultant signature is incorrect, common test systems must execute a complicated series of additional tests to identify the failing scan chain, frequently requiring multiple runs of the exact same test pattern.
Therefore, there is a need for a system and/or method for scan chain fail diagnostics that addresses at least some of the problems and disadvantages associated with conventional systems and methods.